EP2S180F1020C4 Datasheet, PDF (636/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

JTAG Configuration
JTAG
Configuration
f
The JTAG has developed a specification for boundary-scan testing. This
boundary-scan test (BST) architecture offers the capability to efficiently
test components on PCBs with tight lead spacing. The BST architecture
can test pin connections without using physical test probes and capture
functional data while a device is operating normally. The JTAG circuitry
can also be used to shift configuration data into the device. The Quartus II
software automatically generates SOFs that can be used for JTAG
configuration with a download cable in the Quartus II software
programmer.
For more information on JTAG boundary-scan testing, refer to the
following documents:
■ IEEE 1149.1 (JTAG) Boundary-Scan Testing in Stratix II & Stratix II GX
Devices chapter in volume 2 of the Stratix II Device Handbook or the
IEEE 1149.1 (JTAG) Boundary-Scan Testing in Stratix II & Stratix II GX
Devices chapter in volume 2 of the Stratix II GX Device Handbook
■ Jam Programming Support - JTAG Technologies
Stratix II and Stratix II GX devices are designed such that JTAG
instructions have precedence over any device configuration modes.
Therefore, JTAG configuration can take place without waiting for other
configuration modes to complete. For example, if you attempt JTAG
configuration of Stratix II or Stratix II GX devices during PS
configuration, PS configuration is terminated and JTAG configuration
begins.
1 You cannot use the Stratix II and Stratix II GX decompression or
design security features if you are configuring your Stratix II or
Stratix II GX device when using JTAG-based configuration.
A device operating in JTAG mode uses four required pins, TDI, TDO, TMS,
and TCK, and one optional pin, TRST. The TCK pin has an internal weak
pull-down resistor, while the TDI, TMS, and TRST pins have weak
internal pull-up resistors (typically 25 k). The TDO output pin is
powered by V_CCIO in I/O bank 4. All of the JTAG input pins are powered
by the 3.3-V V_CCPD pin. All user I/O pins are tri-stated during JTAG
configuration. Table 7–19 explains each JTAG pin’s function.
1
The TDO output is powered by the V_CCIO power supply of I/O
bank 4.
7–84
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008