EP2S180F1020C4 Datasheet, PDF (491/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

High-Speed Differential I/O Interfaces with DPA in Stratix II and Stratix II GX Devices
other phase shifts in 45° increments. These settings are made statically in
the Quartus II MegaWizard^® software. Figure 5–4 shows the transmitter
in clock output mode.
Figure 5–4. Transmitter in Clock Output Mode
Transmitter Circuit
Parallel
Series
Internal
Logic
tx_outclock
diffioclk
load_en
The serializer can be bypassed to support DDR (2) and SDR (1)
operations. The I/O element (IOE) contains two data output registers that
each can operate in either DDR or SDR mode. The clock source for the
registers in the IOE can come from any routing resource, from the fast
PLL, or from the enhanced PLL. Figure 5–5 shows the bypass path.
Figure 5–5. Serializer Bypass
Internal Logic
IOE Supports SDR, DDR, or
Non-Registered Data Path
IOE
Serializer
tx_out
Not used (connection exists)
Altera Corporation
January 2008
5–7
Stratix II Device Handbook, Volume 2