EP2S180F1020C4 Datasheet, PDF (662/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Functional Description
Functional
Description
The dedicated remote system upgrade circuitry in Stratix II and
Stratix II GX FPGAs manages remote configuration and provides error
detection, recovery, and status information. User logic or a Nios processor
implemented in the FPGA logic array provides access to the remote
configuration data source and an interface to the system’s configuration
memory.
Stratix II and Stratix II GX FPGA’s remote system upgrade process
involves the following steps:
1. A Nios processor (or user logic) implemented in the FPGA logic
array receives new configuration data from a remote location. The
connection to the remote source is a communication protocol such
as the transmission control protocol/Internet protocol (TCP/IP),
peripheral component interconnect (PCI), user datagram protocol
(UDP), universal asynchronous receiver/transmitter (UART), or a
proprietary interface.
2. The Nios processor (or user logic) stores this new configuration data
in non-volatile configuration memory. The non-volatile
configuration memory can be any standard flash memory used in
conjunction with an intelligent host (for example, a MAX^® device or
microprocessor), the serial configuration device, or the enhanced
configuration device.
3. The Nios processor (or user logic) initiates a reconfiguration cycle
with the new or updated configuration data.
4. The dedicated remote system upgrade circuitry detects and recovers
from any error(s) that might occur during or after the
reconfiguration cycle, and provides error status information to the
user design.
8–2
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008