EP2S180F1020C4 Datasheet, PDF (445/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Altera Corporation
January 2008
Selectable I/O Standards in Stratix II and Stratix II GX Devices
operation in conditions where a bus must be isolated from large stubs.
SSTL-2 requires a 1.25-V V_REF and a 1.25-V V_TT to which the series and
termination resistors are connected (Figures 4–1 and 4–2).
1 Stratix II and Stratix II GX devices support both input and
output levels operation.
Figure 4–1. 2.5-V SSTL Class I Termination
Output Buffer
25 Ω
V_TT = 1.25 V
Z = 50 Ω
50 Ω
V_REF = 1.25 V
Input Buffer
Figure 4–2. 2.5-V SSTL Class II Termination
V_TT = 1.25 V
V_TT = 1.25 V
Output Buffer
50 Ω
50 Ω
25 Ω
Z = 50 Ω
V_REF = 1.25 V
Input Buffer
SSTL-18 Class I and SSTL-18 Class II
The 1.8-V SSTL-18 standard is formulated under JEDEC Standard,
JESD8-15: Stub Series Terminated Logic for 1.8-V (SSTL_18).
The SSTL-18 I/O standard is a 1.8-V memory bus standard used for
applications such as high-speed DDR2 SDRAM interfaces. This standard
is similar to SSTL-2 and defines input and output specifications for
devices that are designed to operate in the SSTL-18 logic switching range
0.0 to 1.8 V. SSTL-18 requires a 0.9-V V_REF and a 0.9-V V_TT to which the
series and termination resistors are connected.
There are no class definitions for the SSTL-18 standard in the JEDEC
specification. The specification of this I/O standard is based on an
environment that consists of both series and parallel terminating
resistors. Altera provides solutions to two derived applications in JEDEC
specification, and names them Class I and Class II to be consistent with
other SSTL standards. Figures 4–3 and 4–4 show SSTL-18 Class I and II
termination, respectively.
4–7
Stratix II Device Handbook, Volume 2