EP2S180F1020C4 Datasheet, PDF (704/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

IEEE Std. 1149.1 BST Operation Control
Figure 9–8. IEEE Std. 1149.1 BST SAMPLE/PRELOAD Mode
Capture Phase
In the capture phase, the
signals at the pin, OEJ and
OUTJ, are loaded into the
capture registers. The CLOCK
signals is supplied by the TAP
controller’s CLOCKDR output.
The data retained in these
registers consists of signals
from normal device operation.
0
1
OEJ
0
1
OUTJ
0
1
SDO
DQ
0
INJ
DQ
1
DQ
0
DQ
1
DQ
0
DQ
1
Shift and Update Phases
In the shift phase, the previously
captured signals at the pin, OEJ
and OUTJ, are shifted out of the
boundary-scan register via the
TDO pin using CLOCK. As data is
shifted out, the patterns for the
next test can be shifted in via the
TDI pin.
In the update phase, data is
transferred from the capture to
the UPDATE registers using the
UPDATE clock. The data stored
in the UPDATE registers can be
used for the EXTEST instruction.
Capture
Registers
Update
Registers
SDI
SHIFT
CLOCK
UPDATE
MODE
SDO
0
0
INJ
DQ
DQ
1
1
OEJ
0
1
OUTJ
0
1
DQ
0
DQ
1
DQ
0
DQ
1
Capture
Registers
Update
Registers
SDI
SHIFT
CLOCK
UPDATE
MODE
9–12
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008