EP2S180F1020C4 Datasheet, PDF (297/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Altera Corporation
July 2009
PLLs in Stratix II and Stratix II GX Devices
Figure 1–16. Counter Cascading
VCO Output
C0
VCO Output
C1
VCO Output
C2
VCO Output
C3
VCO Output
C4
VCO Output
C5
When cascading counters to implement a larger division of the
high-frequency VCO clock, the cascaded counters behave as one counter
with the product of the individual counter settings. For example, if C0 = 4
and C1 = 2, then the cascaded value is C0 × C1 = 8.
1 The Stratix II and Stratix II GX fast PLLs does not support
counter cascading.
Counter cascading is set in the configuration file, meaning they can not be
cascaded using PLL reconfiguration.
Clock Switchover
The clock switchover feature allows the PLL to switch between two
reference input clocks. Use this feature for clock redundancy or for a dual
clock domain application such as in a system that turns on the redundant
clock if the primary clock stops running. The design can perform clock
switchover automatically, when the clock is no longer toggling, or based
on a user control signal, clkswitch.
1 Enhanced PLLs support both automatic and manual switchover,
while fast PLLs only support manual switchover.
Automatic Clock Switchover
Stratix II and Stratix II GX device PLLs support a fully configurable clock
switchover capability. Figure 1–17 shows the block diagram of the
switch-over circuit built into the enhanced PLL. When the primary clock
signal is not present, the clock sense block automatically switches from
1–33
Stratix II Device Handbook, Volume 2