EP2S180F1020C4 Datasheet, PDF (434/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Enhancements In Stratix II and Stratix II GX Devices
PLL
When using the Stratix II and Stratix II GX top and bottom I/O banks
(I/O banks 3, 4, 7, or 8) to interface with a DDR memory, at least one PLL
with two outputs is needed to generate the system clock and the write
clock. The system clock generates the DQS write signals, commands, and
addresses. The write clock is either shifted by –90° or 90° from the system
clock and is used to generate the DQ signals during writes.
For DDR and DDR2 SDRAM interfaces above 200 MHz, Altera also
recommends a second read PLL to help ease resynchronization.
When using the Stratix II and Stratix II GX side I/O banks 1, 2, 5, or 6 to
interface with DDR SDRAM devices, two PLLs may be needed per I/O
bank for best performance. Since the side I/O banks do not have
dedicated circuitry, one PLL captures data from the DDR SDRAM and
another PLL generates the write signals, commands, and addresses to the
DDR SDRAM device. Stratix II and Stratix II GX side I/O banks can
support DDR SDRAM up to 150 MHz.
Enhancements
In Stratix II and
Stratix II GX
Devices
Stratix II and Stratix II GX external memory interfaces support differs
from Stratix external memory interfaces support in the following ways:
■ A PLL output can now be used as the input reference clock to the
DLL.
■ The shifted DQS signal can now go into the logic array.
■ The DLL in Stratix II and Stratix II GX devices has more phase-shift
options than in Stratix devices. It also has the option to add phase
offset settings.
■ Stratix II and Stratix II GX devices have DQS logic blocks with each
DQS pin that helps with fine tuning the phase shift.
■ The DQS delay settings can be routed from the DLL into the logic
array. You can also bypass the DLL and send the DQS delay settings
from the logic array to the DQS logic block.
■ Stratix II and Stratix II GX devices support DQSn pins.
■ The DQS/DQ groups now support ×4, ×9, ×18, and ×36 bus modes.
■ The DQS pins have been enhanced with the DQS postamble circuitry.
Conclusion
Stratix II and Stratix II GX devices support SDR SDRAM, DDR SDRAM,
DDR2 SDRAM, RLDRAM II, and QDRII SRAM external memories.
Stratix II and Stratix II GX devices feature high-speed interfaces that
transfer data between external memory devices at up to 300 MHz/600
Mbps. DQS phase-shift circuitry and DQS logic blocks within the
Stratix II and Stratix II GX devices allow you to fine-tune the phase shifts
for the input clocks or strobes to properly align clock edges as needed to
capture data.
3–38
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008