EP2S180F1020C4 Datasheet, PDF (492/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Differential Receiver
Differential
Receiver
The receiver has dedicated circuitry to support high-speed LVDS and
HyperTransport signaling, along with enhanced data reception. Each
receiver consists of a differential buffer, dynamic phase aligner (DPA),
synchronization FIFO buffer, data realignment circuit, deserializer, and a
shared fast PLL. The differential buffer receives LVDS or HyperTransport
signal levels, which are statically set by the Quartus II software. The DPA
block aligns the incoming data to one of eight clock phases to maximize
the receiver’s skew margin. The DPA circuit can be bypassed on a
channel-by-channel basis if it is not needed. Set the DPA bypass statically
in the Quartus II MegaWizard Plug-In Manager or dynamically by using
the optional RX_DPLL_ENABLE port.
The synchronizer circuit is a 1-bit wide by 6-bit deep FIFO buffer that
compensates for any phase difference between the DPA block and the
deserializer. If necessary, the data realignment circuit inserts a single bit
of latency in the serial bit stream to align the word boundary. The
deserializer includes shift registers and parallel load registers, and sends
a maximum of 10 bits to the internal logic. The data path in the receiver is
clocked by either the diffioclk signal or the DPA recovered clock. The
deserialization factor can be statically set to 4, 5, 6, 7, 8, 9, or 10 by using
the Quartus II software. The fast PLL automatically generates the load
enable signal, which is derived from the deserialization factor setting.
Figure 5–6 shows a block diagram of the receiver.
Figure 5–6. Receiver Block Diagram
Up to 1 Gbps
+
–
DPA Bypass Multiplexer
DQ
Data
Realignment
Circuitry
Eight Phase Clocks
rx_inclk
data retimed_data
DPA
DPA_clk
Synchronizer
8
Fast
PLL
diffioclk
load_en
Dedicated
Receiver
Interface
10
Internal
Logic
Regional or
Global Clock
5–8
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008