EP2S180F1020C4 Datasheet, PDF (296/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Advanced Features
Advanced
Features
clkena
If the system cannot tolerate the higher output frequencies when using
pfdena higher value, the clkena signals can disable the output clocks
until the PLL locks. The clkena signals control the regional, global, and
external clock outputs. The clkena signals are registered on the falling
edge of the counter output clock to enable or disable the clock without
glitches. See Figure 1–56 in the “Clock Control Block” section on
page 1–86 of this document for more information about the clkena
signals.
Stratix II and Stratix II GX PLLs offer a variety of advanced features, such
as counter cascading, clock switchover, PLL reconfiguration,
reconfigurable bandwidth, and spread-spectrum clocking. Table 1–14
shows which advanced features are available in which type of Stratix II or
Stratix II GX PLL.
Table 1–14. Stratix II and Stratix II GX PLL Advanced Features
Advanced Feature
Counter cascading
Clock switchover
PLL reconfiguration
Reconfigurable bandwidth
Spread-spectrum clocking
Availability
Enhanced PLLs
v
v
v
v
v
Fast PLLs (1)
v
v
v
Note to Table 1–14:
(1) Stratix II and Stratix II GX fast PLLs only support manual clock switchover, not
automatic clock switchover.
Counter Cascading
The Stratix II and Stratix II GX enhanced PLL supports counter cascading
to create post-scale counters larger than 512. This is implemented by
feeding the output of one counter into the input of the next counter in a
cascade chain, as shown in Figure 1–16.
1–32
Stratix II Device Handbook, Volume 2
Altera Corporation
July 2009