EP2S180F1020C4 Datasheet, PDF (4/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Contents
Stratix II Device Handbook, Volume 1
Open-Drain Output ........................................................................................................................ 2–84
Bus Hold .......................................................................................................................................... 2–84
Programmable Pull-Up Resistor .................................................................................................. 2–85
Advanced I/O Standard Support ................................................................................................ 2–85
On-Chip Termination .................................................................................................................... 2–89
MultiVolt I/O Interface ................................................................................................................. 2–93
High-Speed Differential I/O with DPA Support ............................................................................ 2–96
Dedicated Circuitry with DPA Support .................................................................................... 2–100
Fast PLL & Channel Layout ........................................................................................................ 2–102
Document Revision History ............................................................................................................. 2–104
Chapter 3. Configuration & Testing
IEEE Std. 1149.1 JTAG Boundary-Scan Support ............................................................................... 3–1
SignalTap II Embedded Logic Analyzer ............................................................................................ 3–4
Configuration ......................................................................................................................................... 3–4
Operating Modes .............................................................................................................................. 3–5
Configuration Schemes ................................................................................................................... 3–7
Configuring Stratix II FPGAs with JRunner ............................................................................... 3–10
Programming Serial Configuration Devices with SRunner ..................................................... 3–10
Configuring Stratix II FPGAs with the MicroBlaster Driver ................................................... 3–11
PLL Reconfiguration ...................................................................................................................... 3–11
Temperature Sensing Diode (TSD) ................................................................................................... 3–11
Automated Single Event Upset (SEU) Detection ............................................................................ 3–13
Custom-Built Circuitry .................................................................................................................. 3–14
Software Interface ........................................................................................................................... 3–14
Document Revision History ............................................................................................................... 3–14
Chapter 4. Hot Socketing & Power-On Reset
Stratix II
Hot-Socketing Specifications ............................................................................................................... 4–1
Devices Can Be Driven Before Power-Up .................................................................................... 4–2
I/O Pins Remain Tri-Stated During Power-Up ........................................................................... 4–2
Signal Pins Do Not Drive the V_CCIO, V_CCINT or V_CCPD Power Supplies .................................... 4–2
Hot Socketing Feature Implementation in Stratix II Devices .......................................................... 4–3
Power-On Reset Circuitry .................................................................................................................... 4–5
Document Revision History ................................................................................................................. 4–6
Chapter 5. DC & Switching Characteristics
Operating Conditions ........................................................................................................................... 5–1
Absolute Maximum Ratings ........................................................................................................... 5–1
Recommended Operating Conditions .......................................................................................... 5–2
DC Electrical Characteristics .......................................................................................................... 5–3
I/O Standard Specifications ........................................................................................................... 5–4
Bus Hold Specifications ................................................................................................................. 5–17
On-Chip Termination Specifications ........................................................................................... 5–17
Pin Capacitance .............................................................................................................................. 5–19
Power Consumption ........................................................................................................................... 5–20
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