EP2S180F1020C4 Datasheet, PDF (281/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

PLLs in Stratix II and Stratix II GX Devices
Table 1–8. Fast PLL Input Signals (Part 2 of 2)
Name
pllena
clkswitch
areset
pfdena
scanclk
scandata
scanwrite
scanread
Description
Source
Enable pin for enabling or disabling all or a set Pin
of PLLs. Active high.
Switch-over signal used to initiate external clock Logic array
switch-over control. Active high.
Enables the up/down outputs from the
phase-frequency detector. Active high.
Logic array
Enables the up/down outputs from the
phase-frequency detector. Active high.
Logic array
Serial clock signal for the real-time PLL control Logic array
feature.
Serial input data stream for the real-time PLL Logic array
control feature.
Enables writing the data in the scan chain into Logic array
the PLL Active high.
Enables scan data to be written into the scan Logic array
chain Active high.
Destination
PLL control signal
Reconfiguration circuit
PLL control signal
PFD
Reconfiguration circuit
Reconfiguration circuit
Reconfiguration circuit
Reconfiguration circuit
Table 1–9. Fast PLL Output Signals
Name
c[3..0]
locked
scandataout
scandone
Description
PLL outputs driving regional or global clock.
Lock or gated lock output from lock detect circuit. Active
high.
Output of the last shift register in the scan chain.
Signal indicating when the PLL has completed
reconfiguration. 1 to 0 transition indicates the PLL has
been reconfigured.
Source
Destination
PLL counter
Internal clock
PLL lock detect Logic array
PLL scan chain Logic array
PLL scan chain Logic array
Altera Corporation
July 2009
1–17
Stratix II Device Handbook, Volume 2