EP2S180F1020C4 Datasheet, PDF (222/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Timing Model
Table 5–79. Maximum Output Clock Toggle Rate Derating Factors (Part 4 of 5)
I/O Standard
Drive
Strength
Differential
SSTL-18 Class I
(3)
Differential
SSTL-18 Class II
(3)
1.8-V Differential
HSTL Class I (3)
1.8-V Differential
HSTL Class II (3)
1.5-V Differential
HSTL Class I (3)
1.5-V Differential
HSTL Class II (3)
3.3-V PCI
3.3-V PCI-X
LVDS
4 mA
6 mA
8 mA
10 mA
12 mA
8 mA
16 mA
18 mA
20 mA
4 mA
6 mA
8 mA
10 mA
12 mA
16 mA
18 mA
20 mA
4 mA
6 mA
8 mA
10 mA
12 mA
16 mA
18 mA
20 mA
HyperTransport
technology
LVPECL (4)
Maximum Output Clock Toggle Rate Derating Factors (ps/pF)
Column I/O Pins
Row I/O Pins
Dedicated Clock Outputs
-3
-4
-5
-3
-4
-5
-3 -4
-5
458 570 570
-
-
-
505 570 570
305 380 380
-
-
-
336 380 380
225 282 282
-
-
-
248 282 282
167 220 220
-
-
-
190 220 220
129 175 175
-
-
-
148 175 175
173 206 206
-
-
-
155 206 206
150 160 160
-
-
-
140 160 160
120 130 130
-
-
-
110 130 130
109 127 127
-
-
-
94 127 127
245 282 282
-
-
-
229 282 282
164 188 188
-
-
-
153 188 188
123 140 140
-
-
-
114 140 140
110 124 124
-
-
-
108 124 124
97
110 110
-
-
-
104 110 110
101 104 104
-
-
-
99 104 104
98
102 102
-
-
-
93 102 102
93
99
99
-
-
-
88 99
99
168 196 196
-
-
-
188 196 196
112 131 131
-
-
-
125 131 131
84
99
99
-
-
-
95 99
99
87
98
98
-
-
-
90 98
98
86
98
98
-
-
-
87 98
98
95
101 101
-
-
-
96 101 101
95
100 100
-
-
-
101 100 100
94
101 101
-
-
-
104 101 101
134 177 177
-
-
-
143 177 177
134 177 177
-
-
-
143 177 177
-
-
- 155 (1) 155 155 134 134 134
(1)
(1)
-
-
- 155 (1) 155 155
-
-
-
(1)
(1)
-
-
-
-
-
-
134 134 134
5–76
Stratix II Device Handbook, Volume 1
Altera Corporation
April 2011