EP2S180F1020C4 Datasheet, PDF (562/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Configuration Features
V_CCPD Pins
Stratix II and Stratix II GX devices also offer a new power supply, V_CCPD,
which must be connected to 3.3-V in order to power the 3.3-V/2.5-V
buffer available on the configuration input pins and JTAG pins. V_CCPD
applies to all the JTAG input pins (TCK, TMS, TDI, and TRST) and the
configuration pins when VCCSEL is connected to ground. Refer to
Table 7–5 for information on the pins affected by VCCSEL.
1
V_CCPD must ramp-up from 0-V to 3.3-V within 100 ms. If V_CCPD
is not ramped up within this specified time, your Stratix II or
Stratix II GX device will not configure successfully. If your
system does not allow for a V_CCPD ramp-up time of 100 ms or
less, you must hold nCONFIG low until all power supplies are
stable.
VCCSEL Pin
The VCCSEL pin selects the type of input buffer used on configuration
input pins and it selects the POR trip point voltage level for V_CCIO bank 3
powered by VCCIO3 pins.
1 For more information, refer to Table 7–24 on page 7–105.
The configuration input pins and the PLL_ENA pin (Table 7–5) have a
dual buffer design. These pins have a 3.3-V/2.5-V input buffer and a
1.8-V/1.5-V input buffer. The VCCSEL input pin selects which input
buffer is used during configuration. The 3.3-V/2.5-V input buffer is
powered by V_CCPD, while the 1.8-V/1.5-V input buffer is powered by
V_CCIO. After configuration, the dual-purpose configuration pins are
powered by the V_CCIO pins of the bank in which they reside. Table 7–5
shows the pins affected by VCCSEL.
7–10
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008