EP2S180F1020C4 Datasheet, PDF (294/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Hardware Features
Figure 1–15 shows the timing waveform for the lock and gated lock
signals.
Figure 1–15. Timing Waveform for Lock and Gated Lock Signals
PLL_ENA
Reference Clock
Feedback Clock
Lock
Gated Lock
Filter Counter
Reaches
Value Count
The device resets and enables both the counter and the PLL
simultaneously when the pllena signal is asserted or the areset signal
is de-asserted. Enhanced PLLs and fast PLLs support this feature. To
ensure correct circuit operation, and to ensure that the output clocks have
the correct phase relationship with respect to the input clock, Altera
recommends that the input clock be running before the Stratix II device is
finished configuring.
PLL_ENA
The PLL_ENA pin is a dedicated pin that enables or disables all PLLs on
the Stratix II or Stratix II GX device. When the PLL_ENA pin is low, the
clock output ports are driven low and all the PLLs go out of lock. When
the PLL_ENA pin goes high again, the PLLs relock and resynchronize to
the input clocks. You can choose which PLLs are controlled by the
pllena signal by connecting the pllena input port of the altpll
megafunction to the common PLL_ENA input pin.
Also, whenever the PLL loses lock for any reason (be it excessive inclk
jitter, clock switchover, PLL reconfiguration, power supply noise, etc.),
the PLL must be reset with the areset signal to guarantee correct phase
relationship between the PLL output clocks. If the phase relationship
between the input clock versus output clock, and between different
output clocks from the PLL is not important in your design, the PLL need
not be reset.
1–30
Stratix II Device Handbook, Volume 2
Altera Corporation
July 2009