EP2S180F1020C4 Datasheet, PDF (645/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Configuring Stratix II and Stratix II GX Devices
Table 7–21. Stratix II Configuration Pin Summary (Part 2 of 2) Note (1)
Bank
7
7
4
4
Description
PLL_ENA
nCEO
MSEL[3..0]
TDO
Input/Output
Input
Output
Input
Output
Dedicated
Yes
Yes
Yes
Yes
Powered By
(3)
(2), (4)
VCCINT
(2), (4)
Configuration Mode
Optional
All modes
All modes
JTAG
Notes to Table 7–21:
(1) Total number of pins is 41, total number of dedicated pins is 19.
(2) All outputs are powered by VCCIO except as noted.
(3) All inputs are powered by VCCIO or VCCPD, based on the VCCSEL setting, except as noted.
(4) An external pull-up resistor may be required for this configuration pin because of the multivolt I/O interface. Refer
to the Stratix II Architecture chapter in volume 1 of the Stratix II Device Handbook for pull-up or level shifter
recommendations for nCEO and TDO.
Figure 7–38 shows the I/O bank locations.
Figure 7–38. Stratix II I/O Bank Numbers
Bank 3
Bank 4
Stratix II Device
I/O Bank Numbers
Bank 8
Bank 7
Altera Corporation
January 2008
7–93
Stratix II Device Handbook, Volume 2