EP2S180F1020C4 Datasheet, PDF (280/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Fast PLLs
f
External Clock Outputs
Each fast PLL supports differential or single-ended outputs for
source-synchronous transmitters or for general-purpose external clocks.
There are no dedicated external clock output pins. The fast PLL global or
regional outputs can drive any I/O pin as an external clock output pin.
The I/O standards supported by any particular bank determines what
standards are possible for an external clock output driven by the fast PLL
in that bank.
For more information, see the Selectable I/O Standards in Stratix II and
Stratix II GX Devices chapter in volume 2 of the Stratix II GX Device
Handbook (or the Stratix II Device Handbook).
Fast PLL Software Overview
Stratix II and Stratix II GX fast PLLs are enabled in the Quartus II
software by using the altpll megafunction. Figure 1–8 shows the
available ports (as they are named in the Quartus II altpll
megafunction) of the Stratix II or Stratix II GX fast PLL.
Figure 1–8. Stratix II and Stratix II GX Fast PLL Ports and Physical Destinations
inclk0 (1)
inclk1 (1)
pllena (2)
areset
pfdena
scanclk
scandata
scanwrite
scanread
C[3..0]
locked
scandataout
scandone
Notes to Figure 1–8:
(1) This input pin is either single-ended or differential.
(2) This input pin is shared by all enhanced and fast PLLs.
Physical Pin
Signal Driven by Internal Logic
Signal Driven to Internal Logic
Internal Clock Signal
Tables 1–8 and 1–9 show the description of all fast PLL ports.
Table 1–8. Fast PLL Input Signals (Part 1 of 2)
Name
inclk0
inclk1
Description
Primary clock input to the fast PLL.
Secondary clock input to the fast PLL.
Source
Destination
Pin or another PLL n counter
Pin or another PLL n counter
1–16
Stratix II Device Handbook, Volume 2
Altera Corporation
July 2009