|
EP2S180F1020C4 Datasheet, PDF (243/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1 | |||
|
◁ |
DC & Switching Characteristics
Table 5â102 shows the JTAG timing parameters and values for Stratix II
devices.
Table 5â102. Stratix II JTAG Timing Parameters & Values
Symbol
Parameter
Min Max Unit
tJCP
tJCH
tJCL
tJPSU
tJPH
tJPCO
tJPZX
tJPXZ
TCK clock period
TCK clock high time
TCK clock low time
JTAG port setup time
JTAG port hold time
JTAG port clock to output
JTAG port high impedance to valid output
JTAG port valid output to high impedance
30
ns
13
ns
13
ns
3
ns
5
ns
11 (1) ns
14 (1) ns
14 (1) ns
Note to Table 5â102:
(1) A 1 ns adder is required for each VC C I O voltage step down from 3.3 V. For
example, tJPCO = 12 ns if VC C I O of the TDO I/O bank = 2.5 V, or 13 ns if it equals
1.8 V.
Document
Table 5â103 shows the revision history for this chapter.
Revision History
Table 5â103. Document Revision History (Part 1 of 3)
Date and
Document
Version
Changes Made
April 2011, v4.5 Updated Table 5â3.
July 2009, v4.4 Updated Table 5â92.
May 2007, v4.3
â Updated RCONF in Table 5â4.
â Updated fIN (min) in Table 5â92.
â Updated fIN and fINPFD in Table 5â93.
Moved the Document Revision History section to the
end of the chapter.
Summary of Changes
Added operating junction temperature
for military use.
Updated the spread spectrum
modulation frequency (fS S) from
(100 kHzâ500 kHz) to
(30 kHzâ150 kHz).
â
â
Altera Corporation
April 2011
5â97
Stratix II Device Handbook, Volume 1
|
▷ |