EP2S180F1020C4 Datasheet, PDF (342/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Clocking
Tables 1–23 and 1–24 show the global and regional clocks that the PLL
outputs drive.
Table 1–23. Stratix II Global and Regional Clock Outputs From PLLs (Part 1 of 3)
PLL Number and Type
Clock Network
EP2S15 through EP2S30 Devices
Fast PLLs
Enhanced
PLLs
EP2S60 through EP2S180 Devices
Fast PLLs
Enhanced
PLLs
GCLK0
GCLK1
GCLK2
GCLK3
GCLK4
GCLK5
GCLK6
GCLK7
GCLK8
GCLK9
GCLK10
GCLK11
GCLK12
GCLK13
GCLK14
GCLK15
RCLK0
RCLK1
RCLK2
RCLK3
RCLK4
RCLK5
RCLK6
RCLK7
RCLK8
RCLK9
1 2 3 4 5 6 7 8 9 10 11 12
vv
vv
vv
vv
vv
vv
vv
vv
v
v
v
v
v
v
v
v
vv
vv
vv
vv
vv
vv
vv
vv
v
v
v
v
v
v
v
v
vv
v
vv
v
vv
v
vv
v
vv
v
vv
v
vv
v
vv
v
v
v
v
v
1–78
Stratix II Device Handbook, Volume 2
Altera Corporation
July 2009