EP2S180F1020C4 Datasheet, PDF (288/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Clock Feedback Modes
Figure 1–12. Phase Relationship Between PLL Clocks in Zero Delay Buffer
Mode
Phase Aligned
PLL Reference
Clock at the
Input Pin
PLL Clock at the
Register Clock Port
External PLL
Clock Outputs (1)
Note to Figure 1–12:
(1) The internal PLL clock output can lead or lag the external PLL clock outputs.
External Feedback Mode
In the external feedback mode, the external feedback input pin, fbin, is
phase-aligned with the clock input pin, (see Figure 1–13). Aligning these
clocks allows you to remove clock delay and skew between devices. This
mode is possible on all enhanced PLLs. PLLs 5, 6, 11, and 12 support
feedback for one of the dedicated external outputs, either one
single-ended or one differential pair. In this mode, one C counter feeds
back to the PLL fbin input, becoming part of the feedback loop. In this
mode, you will be using one of the dedicated external clock outputs (two
if a differential I/O standard is used) as the PLL fbin input pin. When
using this mode, Altera requires that you use the same I/O standard on
the input clock, feedback input, and output clocks. When using
single-ended I/O standards, the inclk port of the PLL must be fed by the
dedicated CLKp input pin.
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Stratix II Device Handbook, Volume 2
Altera Corporation
July 2009