EP2S180F1020C4 Datasheet, PDF (402/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

External Memory Standards
Figure 3–2. Clock Generation for External Memory Interfaces in Stratix II and Stratix II GX Devices
LE
IOE
V_CC
GND
V_CC
DQ
DQ
CK (1)
DK (2)
V_CC
GND
V_CC
clk
DQ
DQ
CK# (1)
DK# (2)
Notes to Figure 3–2:
(1) CK and CK# are the clocks to the memory devices.
(2) DK and DK# are for RLDRAM II interfaces. You can generate DK# and DK from separate pins if the difference of
the Quartus II software’s reported clock-to-out time for these pins meets the RLDRAM II device’s t_CKDK
specification.
Read and Write Operations
When reading from the memory, DDR and DDR2 SDRAM devices send
the data edge-aligned with respect to the data strobe. To properly read the
data in, the data strobe needs to be center-aligned with respect to the data
inside the FPGA. Stratix II and Stratix II GX devices feature dedicated
circuitry to shift this data strobe to the middle of the data window.
Figure 3–3 shows an example of how the memory sends out the data and
data strobe for a burst-of-two operation.
3–6
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008