EP2S180F1020C4 Datasheet, PDF (377/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

TriMatrix Embedded Memory Blocks in Stratix II and Stratix II GX Devices
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In true dual-port configuration, the RAM outputs can only be configured
for read-during-write mode. This means that during write operation,
data being written to the A or B port of the RAM flows through to the A
or B outputs, respectively. When the output registers are bypassed, the
new data is available on the rising edge of the same clock cycle on which
it was written. Refer to “Read-During-Write Operation at the Same
Address” on page 2–33 for waveforms and information on mixed-port
read-during-write mode.
Potential write contentions must be resolved external to the RAM because
writing to the same address location at both ports results in unknown
data storage at that location. For a valid write operation to the same
address of the M-RAM block, the rising edge of the write clock for port A
must occur following the maximum write cycle time interval after the
rising edge of the write clock for port B. Data is written on the rising edge
of the write clock for the M-RAM block.
Because data is written into the M512 and M4K blocks at the falling edge
of the write clock, the rising edge of the write clock for port A should
occur following half of the maximum write cycle time interval after the
falling edge of the write clock for port B. If this timing is not met, the data
stored in that particular address will be invalid.
Refer to the Stratix II Device Family Data Sheet (volume 1) of the Stratix II
Device Handbook or the Stratix II GX Device Family Data Sheet (volume 1)
of the Stratix II GX Device Handbook for the maximum synchronous write
cycle time.
Altera Corporation
January 2008
2–17
Stratix II Device Handbook, Volume 2