EP2S180F1020C4 Datasheet, PDF(709/768 Page) Altera Corporation – Stratix II Device Handbook, Volume 1

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EP2S180F1020C4 Datasheet, PDF (709/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

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IEEE 1149.1 (JTAG) Boundary-Scan Testing for Stratix II and Stratix II GX Devices

CLAMP Instruction Mode

The CLAMP instruction mode is used to allow the state of the signals

driven from the pins to be determined from the boundary-scan register

while the bypass register is selected as the serial path between the TDI

and TDO ports. The state of all signals driven from the pins are completely

defined by the data held in the boundary-scan register.

1 If you are testing after configuring the device, the

programmable weak pull-up resister or the bus hold feature

overrides the CLAMP value (the value stored in the update

register of the boundary-scan cell) at the pin.

HIGHZ Instruction Mode

The HIGHZ instruction mode sets all of the user I/O pins to an inactive

drive state. These pins are tri-stated until a new JTAG instruction is

executed. When this instruction is loaded into the instruction register, the

bypass register is connected between the TDI and TDO ports.

1 If you are testing after configuring the device, the

programmable weak pull-up resistor or the bus hold feature

overrides the HIGHZ value at the pin.

I/O Voltage

Support in JTAG

Chain

The JTAG chain supports several devices. However, you should use

caution if the chain contains devices that have different VCCIO levels. The

output voltage level of the TDO pin must meet the specifications of the

TDI pin it drives. The TDI pin is powered by VCCPD (3.3 V). For Stratix II

and Stratix II GX devices, the VCCIO power supply of bank 4 powers the

TDO pin. Table 9â3 shows board design recommendations to ensure

proper JTAG chain operation.

You can interface the TDI and TDO lines of the devices that have different

VCCIO levels by inserting a level shifter between the devices. If possible,

you should build the JTAG chain in such a way that a device with a higher

VCCIO level drives to a device with an equal or lower VCCIO level. This

way, a level shifter is used only to shift the TDO level to a level acceptable

to the JTAG tester. Figure 9â13 shows the JTAG chain of mixed voltages

and how a level shifter is inserted in the chain.

Altera Corporation

January 2008

9â17

Stratix II Device Handbook, Volume 2

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