EP2S180F1020C4 Datasheet, PDF (637/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Configuring Stratix II and Stratix II GX Devices
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For recommendations on how to connect a JTAG chain with multiple
voltages across the devices in the chain, refer to the IEEE 1149.1 (JTAG)
Boundary-Scan Testing in Stratix II & Stratix II GX Devices chapter in
volume 2 of the Stratix II Device Handbook or the IEEE 1149.1 (JTAG)
Boundary-Scan Testing in Stratix II & Stratix II GX Devices chapter in
volume 2 of the Stratix II GX Device Handbook.
Table 7–19. Dedicated JTAG Pins
Pin Name Pin Type
Description
TDI
TDO
TMS
TCK
TRST
Test data input
Serial input pin for instructions as well as test and programming data. Data is
shifted in on the rising edge of TCK. If the JTAG interface is not required on the
board, the JTAG circuitry can be disabled by connecting this pin to V_CC.
Test data output
Serial data output pin for instructions as well as test and programming data. Data
is shifted out on the falling edge of TCK. The pin is tri-stated if data is not being
shifted out of the device. If the JTAG circuitry is not used, leave the TDO pin
unconnected.
Test mode select Input pin that provides the control signal to determine the transitions of the TAP
controller state machine. Transitions within the state machine occur on the rising
edge of TCK. Therefore, TMS must be set up before the rising edge of TCK. TMS
is evaluated on the rising edge of TCK. If the JTAG interface is not required on
the board, the JTAG circuitry can be disabled by connecting this pin to V_CC.
Test clock input
The clock input to the BST circuitry. Some operations occur at the rising edge,
while others occur at the falling edge. If the JTAG interface is not required on the
board, the JTAG circuitry can be disabled by connecting this pin to GND.
Test reset input
(optional)
Active-low input to asynchronously reset the boundary-scan circuit. The TRST
pin is optional according to IEEE Std. 1149.1. If the JTAG interface is not required
on the board, the JTAG circuitry can be disabled by connecting this pin to GND.
During JTAG configuration, data can be downloaded to the device on the
PCB through the USB Blaster, MasterBlaster, ByteBlaster II, or
ByteBlasterMV download cable. Configuring devices through a cable is
similar to programming devices in-system, except the TRST pin should be
connected to V_CC. This ensures that the TAP controller is not reset.
Figure 7–35 shows JTAG configuration of a single Stratix II or
Stratix II GX device.
Altera Corporation
January 2008
7–85
Stratix II Device Handbook, Volume 2