EP2S180F1020C4 Datasheet, PDF (446/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Stratix II and Stratix II GX I/O Standards Support
1 Stratix II and Stratix II GX devices support both input and
output levels operation.
Figure 4–3. 1.8-V SSTL Class I Termination
Output Buffer
25 Ω
V_TT = 0.9 V
Z = 50 Ω
50 Ω
V_REF = 0.9 V
Input Buffer
Figure 4–4. 1.8-V SSTL Class II Termination
V_TT = 0.9 V
V_TT = 0.9 V
Output Buffer
50 Ω
50 Ω
25 Ω
Z = 50 Ω
V_REF = 0.9 V
Input Buffer
1.8-V HSTL Class I and 1.8-V HSTL Class II
The HSTL standard is a technology-independent I/O standard
developed by JEDEC to provide voltage scalability. It is used for
applications designed to operate in the 0.0- to 1.8-V HSTL logic switching
range such as quad data rate (QDR) memory clock interfaces.
Although JEDEC specifies a maximum V_CCIO value of 1.6 V, there are
various memory chip vendors with HSTL standards that require a V_CCIO
of 1.8 V. Stratix II and Stratix II GX devices support interfaces to chips
with V_CCIO of 1.8 V for HSTL. Figures 4–5 and 4–6 show the nominal V_REF
and V_TT required to track the higher value of V_CCIO. The value of V_REF is
selected to provide optimum noise margin in the system.
1
Stratix II and Stratix II GX devices support both input and
output levels operation.
4–8
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008