EP2S180F1020C4 Datasheet, PDF (640/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

JTAG Configuration
Table 7–20. Dedicated Configuration Pin Connections During JTAG
Configuration
Signal
Description
nCE
nCEO
On all Stratix II or Stratix II GX devices in the chain, nCE should
be driven low by connecting it to ground, pulling it low via a
resistor, or driving it by some control circuitry. For devices that
are also in multi-device FPP, AS, PS, or PPA configuration
chains, the nCE pins should be connected to GND during JTAG
configuration or JTAG configured in the same order as the
configuration chain.
On all Stratix II or Stratix II GX devices in the chain, nCEO can be
left floating or connected to the nCE of the next device.
MSEL
These pins must not be left floating. These pins support
whichever non-JTAG configuration is used in production. If only
JTAG configuration is used, tie these pins to ground.
nCONFIG
Driven high by connecting to V_CC, pulling up via a resistor, or
driven high by some control circuitry.
nSTATUS
Pull to V_{C C} via a 10-k resistor. When configuring multiple
devices in the same JTAG chain, each nSTATUS pin should be
pulled up to V_{C C} individually.
CONF_DONE
Pull to V_{C C} via a 10-k resistor. When configuring multiple
devices in the same JTAG chain, each CONF_DONE pin should
be pulled up to V_{C C} individually. CONF_DONE going high at the
end of JTAG configuration indicates successful configuration.
DCLK
Should not be left floating. Drive low or high, whichever is more
convenient on your board.
7–88
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008