EP2S180F1020C4 Datasheet, PDF (528/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Architecture
Table 6–5 shows the summary of input register modes for the DSP block.
Table 6–5. Input Register Modes
Register Input
Mode
Parallel input
Shift register input
9×9
v
v
18 × 18
v
v
36 × 36
v
Multiplier Stage
The multiplier stage supports 9 × 9, 18 × 18, or 36 × 36 multipliers as well
as other smaller multipliers in between these configurations. See
“Operational Modes” on page 6–21 for details. Depending on the data
width of the multiplier, a single DSP block can perform many
multiplications in parallel.
Each multiplier operand can be a unique signed or unsigned number.
Two signals, signa and signb, control the representation of each
operand respectively. A logic 1 value on the signa signal indicates that
data A is a signed number while a logic 0 value indicates an unsigned
number. Table 6–6 shows the sign of the multiplication result for the
various operand sign representations. The result of the multiplication is
signed if any one of the operands is a signed value.
Table 6–6. Multiplier Sign Representation
Data A (signa Value)
Unsigned (logic 0)
Unsigned (logic 0)
Signed (logic 1)
Signed (logic 1)
Data B (signb Value)
Unsigned (logic 0)
Signed (logic 1)
Unsigned (logic 0)
Signed (logic 1)
Result
Unsigned
Signed
Signed
Signed
There is only one signa and one signb signal for each DSP block.
Therefore, all of the data A inputs feeding the same DSP block must have
the same sign representation. Similarly, all of the data B inputs feeding the
same DSP block must have the same sign representation. The multiplier
offers full precision regardless of the sign representation.
1 When the signa and signb signals are unused, the Quartus^® II
software sets the multiplier to perform unsigned multiplication
by default.
6–12
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008