EP2S180F1020C4 Datasheet, PDF (500/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Clocking
Figure 5–16. Fast PLL and LVDS/DPA Clocks for EP2SGX60E, EP2SGX90 and EP2SGX130 Devices
Fast
PLL 7
2
4
LVDS
Clock
4
2
Fast
PLL 1
Fast
PLL 2
2
DPA
Clock
Quadrant
Quadrant
No Fast PLLs on
Right Side of
Stratix II GX Devices
LVDS
4
Clock
DPA
Clock
Quadrant
Quadrant
2
Fast
PLL 8
Source Synchronous Timing Budget
This section discusses the timing budget, waveforms, and specifications
for source-synchronous signaling in Stratix II and Stratix II GX devices.
LVDS and HyperTransport I/O standards enable high-speed data
transmission. This high data transmission rate results in better overall
system performance. To take advantage of fast system performance, it is
important to understand how to analyze timing for these high-speed
signals. Timing analysis for the differential block is different from
traditional synchronous timing analysis techniques.
Rather than focusing on clock-to-output and setup times,
source-synchronous timing analysis is based on the skew between the
data and the clock signals. High-speed differential data transmission
requires the use of timing parameters provided by IC vendors and is
strongly influenced by board skew, cable skew, and clock jitter. This
section defines the source-synchronous differential data orientation
timing parameters, the timing budget definitions for Stratix II and
Stratix II GX devices, and how to use these timing parameters to
determine a design's maximum performance.
5–16
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008