EP2S180F1020C4 Datasheet, PDF (701/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

IEEE 1149.1 (JTAG) Boundary-Scan Testing for Stratix II and Stratix II GX Devices
Figure 9–5. IEEE Std. 1149.1 TAP Controller State Machine
TEST_LOGIC/
TMS = 1 RESET
TMS = 0
TMS = 1
RUN_TEST/
TMS = 0
IDLE
TMS = 0
SELECT_DR_SCAN
TMS = 1
TMS = 1 SELECT_IR_SCAN
TMS = 0
TMS = 1
CAPTURE_DR
TMS = 1
CAPTURE_IR
TMS = 0
TMS = 0
SHIFT_DR
TMS = 0
TMS = 1
TMS = 1
EXIT1_DR
TMS = 0
SHIFT_IR
TMS = 0
TMS = 1
EXIT1_IR
TMS = 1
TMS = 0
PAUSE_DR
TMS = 0
TMS = 1
TMS = 0
EXIT2_DR
PAUSE_IR
TMS = 0
TMS = 1
TMS = 0
EXIT2_IR
TMS = 1
TMS = 1
UPDATE_DR
TMS = 0
TMS = 1
TMS = 1
UPDATE_IR
TMS = 0
When the TAP controller is in the TEST_LOGIC/RESET state, the BST
circuitry is disabled, the device is in normal operation, and the instruction
register is initialized with IDCODE as the initial instruction. At device
power-up, the TAP controller starts in this TEST_LOGIC/RESET state. In
addition, forcing the TAP controller to the TEST_LOGIC/RESET state is
done by holding TMS high for five TCK clock cycles or by holding the
TRST pin low. Once in the TEST_LOGIC/RESET state, the TAP controller
remains in this state as long as TMS is held high (while TCK is clocked) or
TRST is held low.
Altera Corporation
January 2008
9–9
Stratix II Device Handbook, Volume 2