EP2S180F1020C4 Datasheet, PDF (505/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

High-Speed Differential I/O Interfaces with DPA in Stratix II and Stratix II GX Devices
Differential Pin
Placement
Guidelines
In order to ensure proper high-speed operation, differential pin
placement guidelines have been established. The Quartus II compiler
automatically checks that these guidelines are followed and will issue an
error message if these guidelines are not met. PLL driving distance
information is separated into guidelines with and without DPA usage.
High-Speed Differential I/Os and Single-Ended I/Os
When a differential channel or channels of side banks are used (with or
without DPA), you must adhere to the guidelines described in the
following sections.
■ Single-ended I/Os are allowed in the same bank as the LVDS
channels (with or without DPA) as long as the single-ended I/O
standard uses the same V_CCIO as the LVDS bank.
■ Single-ended inputs can be in the same LAB row. Outputs cannot be
on the same LAB row with LVDS I/Os. If input registers are used in
the IOE, single-ended inputs cannot be in the same LAB row as an
LVDS SERDES block.
■ LVDS (non-SERDES) I/Os are allowed in the same row as LVDS
SERDES but the use of IOE registers are not allowed.
■ Single-ended outputs are limited to 120 mA drive strength on LVDS
banks (with or without DPA).
● LVTTL equation for maximum number of I/Os in an LVDS
bank:
• 120 mA = (number of LVTTL outputs) × (drive strength of
each LVTTL output)
● SSTL-2 equation:
• 120 mA = (number of SSTL-2 I/Os) × (drive strength of each
output) ÷ 2
● LVTTL and SSTL-2 mix equation:
• 120 mA= (total drive strength of all LVTTL outputs) + (total
drive strength of all SSTL2 outputs) ÷ 2
■ Single-ended inputs can be in the same LAB row as a differential
channel using the SERDES circuitry; however, IOE input registers are
not available for the single-ended I/Os placed in the same LAB row
as differential I/Os. The same rule for input registers applies for non-
SERDES differential inputs placed within the same LAB row as a
SERDES differential channel. The input register must be
implemented within the core logic. The same rule for input registers
applies for non-SERDES differential inputs placed within the same
LAB row as a SERDES differential channel.
Altera Corporation
January 2008
5–21
Stratix II Device Handbook, Volume 2