EP2S180F1020C4 Datasheet, PDF (548/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Software Support
The built-in input shift register chain within the DSP block eliminates the
need for shift registers externally to the DSP block in logic elements (LEs).
This architecture feature simplifies the filter design and improves the
filter performance because all the filter circuitry is localized within the
DSP block.
1 Input shift registers for the 36-bit simple multiplier mode have
to be implemented using external registers to the DSP block.
A single DSP block can implement a four tap 18-bit FIR filter. For filters
larger than four taps, the DSP blocks can be cascaded with additional
adder stages implemented using LEs.
Software
Support
f
f
Altera provides two distinct methods for implementing various modes of
the DSP block in your design: instantiation and inference. Both methods
use the following three Quartus II megafunctions:
■ lpm_mult
■ altmult_add
■ altmult_accum
You can instantiate the megafunctions in the Quartus II software to use
the DSP block. Alternatively, with inference, you can create a HDL design
an synthesize it using a third-party synthesis tool like LeonardoSpectrum
or Synplify or Quartus II Native Synthesis that infers the appropriate
megafunction by recognizing multipliers, multiplier adders, and
multiplier accumulators. Using either method, the Quartus II software
maps the functionality to the DSP blocks during compilation.
See Quartus II On-Line Help for instructions on using the megafunctions
and the MegaWizard Plug-In Manager.
For more information, see the Synthesis section in Design and Synthesis
(volume 1) of the Quartus II Development Software Handbook.
Conclusion
The Stratix II and Stratix II GX device DSP blocks are optimized to
support DSP applications requiring high data throughput such as FIR
filters, FFT functions and encoders. These DSP blocks are flexible and can
be configured to implement one of several operational modes to suit a
particular application. The built-in shift register chain,
adder/subtractor/accumulator block and the summation block
minimizes the amount of external logic required to implement these
functions, resulting in efficient resource utilization and improved
performance and data throughput for DSP applications. The Quartus II
6–32
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008