EP2S180F1020C4 Datasheet, PDF (364/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

TriMatrix Memory Overview
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Refer to the Using Parity to Detect Memory Errors white paper for more
information on using the parity bit to detect memory errors.
Byte Enable Support
All TriMatrix memory blocks support byte enables that mask the input
data so that only specific bytes, nibbles, or bits of data are written. The
unwritten bytes or bits retain the previous written value. The write enable
(wren) signals, along with the byte enable (byteena) signals, control the
RAM blocks’ write operations. The default value for the byte enable
signals is high (enabled), in which case writing is controlled only by the
write enable signals. There is no clear port to the byte enable registers.
M512 Blocks
M512 blocks support byte enables for data widths of 16 and 18 bits only.
For memory block configurations with widths of less than two bytes
(×16/×18), the byte-enable feature is not supported. For memory
configurations less than two bytes wide, the write enable or clock enable
signals can optionally be used to control the write operation. Table 2–4
summarizes the byte selection.
Table 2–4. Byte Enable for Stratix II and Stratix II GX M512 Blocks Note (1)
byteena[1..0]
[0] = 1
[1] = 1
data ×16
[7..0]
[15..8]
data ×18
[8..0]
[17..9]
Note to Table 2–4:
(1) Any combination of byte enables is possible.
M4K Blocks
M4K blocks support byte enables for any combination of data widths of
16, 18, 32, and 36 bits only. For memory block configurations with widths
of less than two bytes (×16/×18), the byte-enable feature is not supported.
For memory configurations less than two bytes wide, the write enable or
clock enable signals can optionally be used to control the write operation.
2–4
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008