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EP2S180F1020C4 Datasheet, PDF (257/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1 | |||
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Contents
Contents
Section VI. PCB Layout Guidelines
Revision History .................................................................................................................... Section VIâ1
Chapter 10. Package Information for Stratix II & Stratix II GX Devices
Introduction .......................................................................................................................................... 10â1
Thermal Resistance .............................................................................................................................. 10â2
Package Outlines ................................................................................................................................. 10â5
484-Pin FBGA - Flip Chip .............................................................................................................. 10â5
672-Pin FBGA - Flip Chip .............................................................................................................. 10â6
780-Pin FBGA - Flip Chip .............................................................................................................. 10â9
1,020-Pin FBGA - Flip Chip ......................................................................................................... 10â11
1,152-Pin FBGA - Flip Chip ......................................................................................................... 10â13
1,508-Pin FBGA - Flip Chip ......................................................................................................... 10â15
Document Revision History ............................................................................................................. 10â17
Chapter 11. High-Speed Board Layout Guidelines
Introduction .......................................................................................................................................... 11â1
PCB Material Selection ........................................................................................................................ 11â1
Transmission Line Layout .................................................................................................................. 11â3
Impedance Calculation .................................................................................................................. 11â4
Propagation Delay .......................................................................................................................... 11â8
Pre-Emphasis .................................................................................................................................. 11â9
Routing Schemes for Minimizing Crosstalk & Maintaining Signal Integrity ........................... 11â11
Signal Trace Routing .................................................................................................................... 11â13
Termination Schemes ........................................................................................................................ 11â19
Simple Parallel Termination ....................................................................................................... 11â19
Thevenin Parallel Termination ................................................................................................... 11â20
Active Parallel Termination ........................................................................................................ 11â21
Series-RC Parallel Termination .................................................................................................. 11â22
Series Termination ....................................................................................................................... 11â23
Differential Pair Termination ..................................................................................................... 11â23
Simultaneous Switching Noise ........................................................................................................ 11â24
Power Filtering & Distribution ................................................................................................... 11â26
Electromagnetic Interference (EMI) ................................................................................................ 11â28
Additional FPGA-Specific Information .......................................................................................... 11â29
Configuration ................................................................................................................................ 11â29
JTAG ............................................................................................................................................... 11â30
Test Point ....................................................................................................................................... 11â30
Summary ............................................................................................................................................. 11â30
References ........................................................................................................................................... 11â31
Document Revision History ............................................................................................................. 11â31
Altera Corporation
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