EP2S180F1020C4 Datasheet, PDF (700/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

IEEE Std. 1149.1 BST Operation Control
f
■ CLAMP instruction mode is used to allow the state of the signals
driven from the pins to be determined from the boundary-scan
register while the bypass register is selected as the serial path
between the TDI and TDO ports
■ HIGHZ instruction mode sets all of the user I/O pins to an inactive
drive state
The BST instruction length is 10 bits. These instructions are described
later in this chapter.
For summaries of the BST instructions and their instruction codes, refer
to the Configuration & Testing chapter in volume 1 of the Stratix II Device
Handbook, or the Configuration & Testing chapter in volume 1 of the
Stratix II GX Device Handbook.
The IEEE Std. 1149.1 TAP controller, a 16-state state machine clocked on
the rising edge of TCK, uses the TMS pin to control IEEE Std. 1149.1
operation in the device. Figure 9–5 shows the TAP controller state
machine.
9–8
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008