EP2S180F1020C4 Datasheet, PDF (652/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Device Configuration Pins
Table 7–22. Dedicated Configuration Pins on the Stratix II and Stratix II GX Device (Part 7 of 10)
Pin Name
DCLK
User Mode
Configuration
Scheme
Pin Type
Description
N/A
Synchronous Input (PS, In PS and FPP configuration, DCLK is the
configuration FPP) Output clock input used to clock data from an external
schemes (PS,
(AS)
source into the target device. Data is latched
FPP, AS)
into the device on the rising edge of DCLK.
In AS mode, DCLK is an output from the
Stratix II or Stratix II GX device that provides
timing for the configuration interface. In AS
mode, DCLK has an internal pull-up resistor
(typically 25 k) that is always active.
In PPA mode, DCLK should be tied high to V_CC
to prevent this pin from floating.
DATA0
After configuration, this pin is tri-stated. In
schemes that use a configuration device,
DCLK will be driven low after configuration is
done. In schemes that use a control host,
DCLK should be driven either high or low,
whichever is more convenient. Toggling this
pin after configuration does not affect the
configured device.
I/O
PS, FPP, PPA,
Input
Data input. In serial configuration modes,
AS
bit-wide configuration data is presented to the
target device on the DATA0 pin.
The V_{I H} and V_{I L} levels for this pin are
dependent on the input buffer selected by the
VCCSEL pin. Refer to the section “VCCSEL
Pin” on page 7–10 for more information.
In AS mode, DATA0 has an internal pull-up
resistor that is always active.
After configuration, DATA0 is available as a
user I/O pin and the state of this pin depends
on the Dual-Purpose Pin settings.
After configuration, EPC1 and EPC1441
devices tri-state this pin, while enhanced
configuration and EPC2 devices drive this pin
high.
7–100
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008