EP2S180F1020C4 Datasheet, PDF (534/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Architecture
Accumulator
When the adder/subtractor/accumulator is configured as an
accumulator, the output of the adder/output block feeds back to the
accumulator as shown in Figure 6–7. The accumulator can be set up to
perform addition only, subtraction only or the addnsub signal can be
used to dynamically control the accumulation direction. A logic 1 value
on the addnsub signal indicates that the accumulator is performing
addition while a logic 0 value indicates subtraction.
Each accumulator can be cleared by either clearing the DSP block output
register or by using the accum_sload signal. The accumulator clear
using the accum_sload signal is independent from the resetting of the
output registers so the accumulation can be cleared and a new one can
begin without losing any clock cycles. The accum_sload signal controls
a feedback multiplexer that specifies that the output of the multiplier
should be summed with a zero instead of the accumulator feedback path.
The accumulator can also be initialized/preloaded with a non-zero value
using the accum_sload signal and the accum_sload_upper_data
bus with one clock cycle latency. Preloading the accumulator is done by
adding the result of the multiplier with the value specified on the
accum_sload_upper_data bus. As in the case of the accumulator
clearing, the accum_sload signal specifies to the feedback multiplexer
that the accum_sload_upper_data signal should feed the
accumulator instead of the accumulator feedback signal. The
accum_sload_upper_data signal only loads the upper 36-bits of the
accumulator. To load the entire accumulator, the value for the lower
16-bits must be sent through the multiplier feeding that accumulator with
the multiplier set to perform a multiplication by one.
The overflow signal will go high on the positive edge of the clock when
the accumulator detects an overflow or underflow. The overflow signal
will stay high for only one clock cycle after an overflow or underflow is
detected even if the overflow or underflow condition is still present. A
latch external to the DSP block has to be used to preserve the overflow
signal indefinitely or until the latch is cleared.
The DSP blocks support Q1.15 input format saturation and rounding in
each accumulator. The following signals are available that can control if
saturation or rounding or both is performed to the output of the
accumulator:
■ accum_round
■ accum_saturation
■ accum_is_saturated output
6–18
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008