EP2S180F1020C4 Datasheet, PDF (338/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Clocking
The clock input multiplexer control signals for performing clock
switchover are from core signals. Figure 1–44 shows the clock input
multiplexer control circuit for a center fast PLL.
Figure 1–44. Center Fast PLL Clock Input Multiplexer Control
core_inclk
clk[3..0] ⁴
core_inclk
(1)
inclk0
inclk1
(1)
To the Clock
Switchover
Block
Note to Figure 1–44:
(1) The input clock multiplexing is controlled through a configuration file only and
cannot be dynamically controlled in user mode.
Each corner fast PLL has three clock input sources, one from a dedicated
corner clock input pin, one from a center clock input pin, and one from a
logic array clock, provided the logic array signal is driven by an output
from another PLL, a pin-driven dedicated global or regional clock, or
through a clock control block, provided the clock control block is fed by
an output from another PLL or a pin-driven dedicated global or regional
clock. An internally generated global signal cannot drive the PLL.
Figure 1–45 shows a block diagram showing the clock input multiplexer
control circuit for a corner fast PLL. Only the corner FPLLCLK pin is fully
compensated.
Figure 1–45. Corner Fast PLL Clock Input Multiplexer Control
core_inclk
(1)
FPLLCLK
4
Center
Clocks
inclk0
inclk1
(1)
To the Clock
Switchover
Block
core_inclk
Note to Figure 1–45:
(1) The input clock multiplexing is controlled through a configuration file only and
cannot be dynamically controlled in user mode.
1–74
Stratix II Device Handbook, Volume 2
Altera Corporation
July 2009