EP2S180F1020C4 Datasheet, PDF (295/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

PLLs in Stratix II and Stratix II GX Devices
f
The level of the VCCSEL pin selects the PLL_ENA input buffer power.
Therefore, if VCCSEL is high, the PLL_ENA pin’s 1.8/1.5-V input buffer is
powered by V_CCIO of the bank that PLL_ENA resides in. If VCCSEL is low
(GND), the PLL_ENA pin’s 3.3/2.5-V input buffer is powered by V_CCPD.
For more information about the VCCSEL pin, refer to the Configuring
Stratix II and Stratix II GX Devices chapter in volume 2 of the Stratix II GX
Device Handbook (or the Stratix II Device Handbook).
pfdena
The pfdena signals control the phase frequency detector (PFD) output
with a programmable gate. If you disable the PFD, the VCO operates at
its last set value of control voltage and frequency with some long-term
drift to a lower frequency. The system continues running when the PLL
goes out of lock or the input clock is disabled. By maintaining the last
locked frequency, the system has time to store its current settings before
shutting down. You can either use your own control signal or clkloss
or gated locked status signals, to trigger pfdena.
areset
The areset signal is the reset or resynchronization input for each PLL.
The device input pins or internal logic can drive these input signals.
When driven high, the PLL counters reset, clearing the PLL output and
placing the PLL out of lock. The VCO is set back to its nominal setting
(~700 MHz). When driven low again, the PLL will resynchronize to its
input as it relocks. If the target VCO frequency is below this nominal
frequency, then the output frequency starts at a higher value than desired
as the PLL locks.
The areset signal should be asserted every time the PLL loses lock to
guarantee correct phase relationship between the PLL input clock and
output clocks. Users should include the areset signal in designs if any
of the following conditions are true:
■ PLL reconfiguration or clock switchover enabled in the design.
■ Phase relationships between the PLL input clock and output clocks
need to be maintained after a loss of lock condition.
■ If the input clock to the PLL is not toggling or is unstable upon power
up, assert the areset signal after the input clock is toggling, making
sure to stay within the input jitter specification.
1
Altera recommends that you use the areset and locked
signals in your designs to control and observe the status of your
PLL.
Altera Corporation
July 2009
1–31
Stratix II Device Handbook, Volume 2