EP2S180F1020C4 Datasheet, PDF (658/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Conclusion
Table 7–24. Dedicated JTAG Pins (Part 2 of 2)
Pin Name User Mode Pin Type
Description
TCK
N/A
Input The clock input to the BST circuitry. Some operations occur at the rising
edge, while others occur at the falling edge. The TCK pin is powered by the
3.3-V V_{C C P D} supply.
TRST
If the JTAG interface is not required on the board, the JTAG circuitry can be
disabled by connecting TCK to GND.
N/A
Input Active-low input to asynchronously reset the boundary-scan circuit. The
TRST pin is optional according to IEEE Std. 1149.1. The TRST pin is
powered by the 3.3-V V_{C C P D} supply.
If the JTAG interface is not required on the board, the JTAG circuitry can be
disabled by connecting the TRST pin to GND.
Conclusion
Referenced
Documents
Stratix II and Stratix II GX devices can be configured in a number of
different schemes to fit your system’s need. In addition, configuration
bitstream encryption, configuration data decompression, and remote
system upgrade support supplement the Stratix II and Stratix II GX
configuration solution.
This chapter references the following documents:
■ AN 122: Using Jam STAPL for ISP & ICR via an Embedded Processor
■ AN 418: SRunner: An Embedded Solution for Serial Configuration Device
Programming
■ ByteBlaster II Download Cable User Guide
■ ByteBlasterMV Download Cable User Guide
■ Configuration Devices for SRAM-Based LUT Devices Data Sheet chapter
in volume 2 of the Configuration Handbook.
■ Configuring Mixed Altera FPGA Chains in volume 2 of the
Configuration Handbook
■ DC & Switching Characteristics chapter in volume 1 of the Stratix II
Device Handbook
■ DC & Switching Characteristics chapter in volume 1 of the Stratix II GX
Device Handbook
■ Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet in
volume 2 of the Configuration Handbook
■ IEEE 1149.1 (JTAG) Boundary-Scan Testing in Stratix II & Stratix II GX
Devices chapter in volume 2 of the Stratix II Device Handbook
■ IEEE 1149.1 (JTAG) Boundary-Scan Testing in Stratix II & Stratix II GX
Devices chapter in volume 2 of the Stratix II GX Device Handbook
■ Jam Programming Support - JTAG Technologies
■ MasterBlaster Serial/USB Communications Cable User Guide
7–106
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008