EP2S180F1020C4 Datasheet, PDF (765/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

High-Speed Board Layout Guidelines
Therefore, placing ground planes close to a signal source reduces
inductance and helps contain EMI. Figure 11–36 shows an example of an
eight-layer stack-up. In the stack-up, the stripline signal layers are the
quietest because they are centered by power and GND planes. A solid
ground plane next to the power plane creates a set of low ESR capacitors.
With integrated circuit edge rates becoming faster and faster, these
techniques help to contain EMI.
Figure 11–36. Example Eight-Layer Stack-Up
Signal
Ground
Signal
Power
Ground
Signal
Ground
Signal
Additional
FPGA-Specific
Information
Component selection and proper placement on the board is important to
controlling EMI.
The following guidelines can reduce EMI:
■ Select low-inductance components, such as surface mount capacitors
with low ESR, and effective series inductance.
■ Use proper grounding for the shortest current return path.
■ Use solid ground planes next to power planes.
■ In unavoidable circumstances, use respective ground planes next to
each segmented power plane for analog and digital circuits.
This section provides the following additional information
recommended by Altera for board design and signal integrity:
FPGA-specific configuration, Joint Test Action Group (JTAG) testing, and
permanent test points.
Configuration
The DCLK signal is used in configuration devices and passive serial (PS)
and passive parallel synchronous (PPS) configuration schemes. This
signal drives edge-triggered pins in Altera devices. Therefore, any
overshoot, undershoot, ringing, crosstalk, or other noise can affect
configuration. Use the same guidelines for designing clock signals to
Altera Corporation
May 2007
11–29
Stratix II Device Handbook, Volume 2