EP2S180F1020C4 Datasheet, PDF (512/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Conclusion
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To achieve the best performance from the device, pay attention to the
impedances of traces and connectors, differential routing, and
termination techniques.
Use this section together with the Stratix II Device Family Data Sheet in
volume 1 of the Stratix II Device Handbook.
The Stratix II and Stratix II GX high-speed module generates signals that
travel over the media at frequencies as high as one Gbps. Board designers
should use the following guidelines:
■ Base board designs on controlled differential impedance. Calculate
and compare all parameters such as trace width, trace thickness, and
the distance between two differential traces.
■ Place external reference resistors as close to receiver input pins as
possible.
■ Use surface mount components.
■ Avoid 90° or 45° corners.
■ Use high-performance connectors such as HMZD or VHDM
connectors for backplane designs. Two suppliers of high-
performance connectors are Teradyne Corp (www.teradyne.com)
and Tyco International Ltd. (www.tyco.com).
■ Design backplane and card traces so that trace impedance matches
the connector’s or the termination’s impedance.
■ Keep an equal number of vias for both signal traces.
■ Create equal trace lengths to avoid skew between signals. Unequal
trace lengths also result in misplaced crossing points and system
margins when the TCCS value increases.
■ Limit vias, because they cause impedance discontinuities.
■ Use the common bypass capacitor values such as 0.001, 0.01, and
0.1 F to decouple the fast PLL power and ground planes. You can
also use 0.0047 F and 0.047 F.
■ Keep switching TTL signals away from differential signals to avoid
possible noise coupling.
■ Do not route TTL clock signals to areas under or above the
differential signals.
■ Route signals on adjacent layers orthogonally to each other.
Conclusion
Stratix II and Stratix II GX high-speed differential inputs and outputs,
with their DPA and data realignment circuitry, allow users to build a
robust multi-Gigabit system. The DPA circuitry allows users to
compensate for any timing skews resulting from physical layouts. The
data realignment circuitry allows the devices to align the data packet
between the transmitter and receiver. Together with the on-chip
differential termination, Stratix II and Stratix II GX devices can be used as
a single-chip solution for high-speed applications.
5–28
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008