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EP2S180F1020C4 Datasheet, PDF (5/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1 | |||
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Contents
Contents
Timing Model ....................................................................................................................................... 5â20
Preliminary & Final Timing .......................................................................................................... 5â20
I/O Timing Measurement Methodology .................................................................................... 5â21
Performance .................................................................................................................................... 5â27
Internal Timing Parameters .......................................................................................................... 5â34
Stratix II Clock Timing Parameters .............................................................................................. 5â41
Clock Network Skew Adders ....................................................................................................... 5â50
IOE Programmable Delay ............................................................................................................. 5â51
Default Capacitive Loading of Different I/O Standards .......................................................... 5â52
I/O Delays ....................................................................................................................................... 5â54
Maximum Input & Output Clock Toggle Rate .......................................................................... 5â66
Duty Cycle Distortion ......................................................................................................................... 5â77
DCD Measurement Techniques ................................................................................................... 5â78
High-Speed I/O Specifications .......................................................................................................... 5â87
PLL Timing Specifications .................................................................................................................. 5â91
External Memory Interface Specifications ....................................................................................... 5â94
JTAG Timing Specifications ............................................................................................................... 5â96
Document Revision History ............................................................................................................... 5â97
Chapter 6. Reference & Ordering Information
Software .................................................................................................................................................. 6â1
Device Pin-Outs ..................................................................................................................................... 6â1
Ordering Information ........................................................................................................................... 6â1
Document Revision History ................................................................................................................. 6â2
Altera Corporation
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