EP2S180F1020C4 Datasheet, PDF (752/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Routing Schemes for Minimizing Crosstalk & Maintaining Signal Integrity
Figure 11–17. Stub Length = Zero Inches
Daisy Chain Routing without Stubs
Figure 11–18 shows daisy chain routing with the main bus running
through the device pins, eliminating stubs. This layout removes the risk
of impedance mismatch between the main bus and the stubs, minimizing
signal integrity problems.
Figure 11–18. Daisy Chain Routing without Stubs
Main Bus
Device 1
Device 2
Clock
Source
Termination
Resistor
Device Pin
(BGA Ball)
Star Routing
In star routing, the clock signal travels to all the devices at the same time
(see Figure 11–19). Therefore, all trace lengths between the clock source
and devices must be matched to minimize the clock skew. Each load
should be identical to minimize signal integrity problems. In star routing,
you must match the impedance of the main bus with the impedance of the
long trace that connects to multiple devices.
11–16
Stratix II Device Handbook, Volume 2
Altera Corporation
May 2007