EP2S180F1020C4 Datasheet, PDF (278/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Enhanced PLLs
Table 1–7. Stratix II and Stratix II GX Enhanced PLL Pins (Part 2 of 3) Note (1)
Pin
PLL6_FBp/n
PLL11_FBp/n
PLL12_FBp/n
PLL_ENA
PLL5_OUT[2..0]p/n
PLL6_OUT[2..0]p/n
PLL11_OUT[2..0]p/n
PLL12_OUT[2..0]p/n
VCCA_PLL5
GNDA_PLL5
VCCA_PLL6
GNDA_PLL6
VCCA_PLL11
GNDA_PLL11
VCCA_PLL12
GNDA_PLL12
VCCD_PLL
VCC_PLL5_OUT
VCC_PLL6_OUT
VCC_PLL11_OUT
Description
Single-ended or differential pins that can drive the fbin port for PLL 6.
Single-ended or differential pins that can drive the fbin port for PLL 11.
Single-ended or differential pins that can drive the fbin port for PLL 12.
Dedicated input pin that drives the pllena port of all or a set of PLLs. If you do
not use this pin, connect it to ground.
Single-ended or differential pins driven by C[5..0] ports from PLL 5.
Single-ended or differential pins driven by C[5..0] ports from PLL 6.
Single-ended or differential pins driven by C[5..0] ports from PLL 11.
Single-ended or differential pins driven by C[5..0] ports from PLL 12.
Analog power for PLL 5. You must connect this pin to 1.2 V, even if the PLL is not
used.
Analog ground for PLL 5. You can connect this pin to the GND plane on the board.
Analog power for PLL 6. You must connect this pin to 1.2 V, even if the PLL is not
used.
Analog ground for PLL 6. You can connect this pin to the GND plane on the board.
Analog power for PLL 11. You must connect this pin to 1.2 V, even if the PLL is not
used.
Analog ground for PLL 11. You can connect this pin to the GND plane on the
board.
Analog power for PLL 12. You must connect this pin to 1.2 V, even if the PLL is not
used.
Analog ground for PLL 12. You can connect this pin to the GND plane on the
board.
Digital power for PLLs. You must connect this pin to 1.2 V, even if the PLL is not
used.
External clock output V_CCIO power for PLL5_OUT0p, PLL5_OUT0n,
PLL5_OUT1p, PLL5_OUT1n, PLL5_OUT2p, and PLL5_OUT2n outputs from
PLL 5.
External clock output V_CCIO power for PLL6_OUT0p, PLL6_OUT0n,
PLL6_OUT1p, PLL6_OUT1n and PLL6_OUT2p, PLL6_OUT2n outputs from
PLL 6.
External clock output V_CCIO power for PLL11_OUT0p, PLL11_OUT0n,
PLL11_OUT1p, PLL11_OUT1n and PLL11_OUT2p, PLL11_OUT2n outputs
from PLL 11.
1–14
Stratix II Device Handbook, Volume 2
Altera Corporation
July 2009