EP2S180F1020C4 Datasheet, PDF (380/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Clock Modes
ROM Mode
M512 and M4K memory blocks support ROM mode. A memory
initialization file (.mif) initializes the ROM contents of these blocks. The
address lines of the ROM are registered. The outputs can be registered or
unregistered. The ROM read operation is identical to the read operation
in the single-port RAM configuration.
f
FIFO Buffers Mode
TriMatrix memory blocks support the FIFO mode. M512 memory blocks
are ideal for designs with many shallow FIFO buffers. All memory
configurations have synchronous inputs; however, the FIFO buffer
outputs are always combinational. Simultaneous read and write from an
empty FIFO buffer is not supported.
Refer to the Single- and Dual-Clock FIFO Megafunctions User Guide and
FIFO Partitioner Megafunction User Guide for more information on FIFO
buffers.
Clock Modes
Depending on which TriMatrix memory mode is selected, the following
clock modes are available:
■ Independent
■ Input/output
■ Read/write
■ Single-clock
Table 2–14 shows these clock modes supported by all TriMatrix blocks
when configured as respective memory modes.
Table 2–14. Stratix II and Stratix II GX TriMatrix Memory Clock Modes
Clocking Modes
Independent
Input/output
Read/write
Single clock
True Dual-Port
Mode
v
v
v
Simple Dual-Port
Mode
Single-Port Mode
v
v
v
v
v
2–20
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008