EP2S180F1020C4 Datasheet, PDF (362/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

TriMatrix Memory Overview
Table 2–1 summarizes the features supported by the three sizes of
TriMatrix memory.
Table 2–1. Summary of TriMatrix Memory Features
Feature
Maximum performance
Total RAM bits (including parity bits)
Configurations
Parity bits
Byte enable
Pack mode
Address clock enable
Single-port memory
Simple dual-port memory
True dual-port memory
Embedded shift register
ROM
FIFO buffer
Simple dual-port mixed width support
True dual-port mixed width support
Memory initialization file (.mif)
Mixed-clock mode
Power-up condition
Register clears
Same-port read-during-write
Mixed-port read-during-write
M512 Blocks
M4K Blocks
M-RAM Blocks
500 MHz
550 MHz
420 MHz
576
4,608
589,824
512 × 1
256 × 2
128 × 4
64 × 8
64 × 9
32 × 16
32 × 18
4K × 1
2K × 2
1K × 4
512 × 8
512 × 9
256 × 16
256 × 18
128 × 32
128 × 36
64K × 8
64K × 9
32K × 16
32K × 18
16K × 32
8K × 64
8K × 72
4K × 128
4K × 144
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
Outputs cleared
Outputs cleared
Outputs unknown
Output registers only Output registers
only
Output registers
only
New data available at New data available
positive clock edge at positive clock
edge
New data available
at positive clock
edge
Outputs set to
Outputs set to
Unknown output
unknown or old data unknown or old data
2–2
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008