EP2S180F1020C4 Datasheet, PDF (353/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

PLLs in Stratix II and Stratix II GX Devices
The global and regional clock networks that are not used are
automatically powered down through configuration bit settings in the
configuration file (SRAM Object File (.sof) or Programmer Object File
(.pof)) generated by the Quartus II software.
The dynamic clock enable or disable feature allows the internal logic to
control power up or down synchronously on GCLK and RCLK nets,
including dual-regional clock regions. This function is independent of the
PLL and is applied directly on the clock network, as shown in Figure 1–52
on page 1–87 and Figure 1–53 on page 1–88.
The input clock sources and the clkena signals for the global and
regional clock network multiplexers can be set through the Quartus II
software using the altclkctrl megafunction. The dedicated external
clock output pins can also be enabled or disabled using the altclkctrl
megafunction. Figure 1–54 shows the external PLL output clock control
block.
Figure 1–54. Stratix II External PLL Output Clock Control Block
PLL Counter
Outputs (c[5..0])
6
Static Clock Select (1)
Enable/
Disable
Internal
Logic
IOE (2)
Internal
Logic
Static Clock
Select (1)
PLL_OUT
Pin
Notes to Figure 1–54:
(1) These clock select signals can only be set through a configuration file and cannot
be dynamically controlled during user mode operation.
(2) The clock control block feeds to a multiplexer within the PLL_OUT pin’s IOE. The
PLL_OUT pin is a dual-purpose pin. Therefore, this multiplexer selects either an
internal signal or the output of the clock control block.
Altera Corporation
July 2009
1–89
Stratix II Device Handbook, Volume 2