EP2S180F1020C4 Datasheet, PDF (680/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Dedicated Remote System Upgrade Circuitry
Read operations during factory configuration access the contents of the
update register. This feature is used by the user logic to verify that the
page address and watchdog timer settings were written correctly. Read
operations in application configurations access the contents of the control
register. This information is used by the user logic in the application
configuration.
User Watchdog Timer
The user watchdog timer prevents a faulty application configuration
from stalling the device indefinitely. The system uses the timer to detect
functional errors after an application configuration is successfully loaded
into the FPGA.
The user watchdog timer is a counter that counts down from the initial
value loaded into the remote system upgrade control register by the
factory configuration. The counter is 29-bits-wide and has a maximum
count value of 2²⁹. When specifying the user watchdog timer value,
specify only the most significant 12 bits. The granularity of the timer
setting is 2¹⁵ cycles. The cycle time is based on the frequency of the
10-MHz internal oscillator. Table 8–7 specifies the operating range of the
10-MHz internal oscillator.
Table 8–7. 10-MHz Internal Oscillator Specifications
Minimum
5
Typical
6.5
Maximum
10
Units
MHz
The user watchdog timer begins counting once the application
configuration enters FPGA user mode. This timer must be periodically
reloaded or reset by the application configuration before the timer expires
by asserting RU_nRSTIMER. If the application configuration does not
reload the user watchdog timer before the count expires, a time-out signal
is generated by the remote system upgrade dedicated circuitry. The
time-out signal tells the remote system upgrade circuitry to set the user
watchdog timer status bit (Wd) in the remote system upgrade status
register and reconfigures the device by loading the factory configuration.
The user watchdog timer is not enabled during the configuration cycle of
the FPGA. Errors during configuration are detected by the CRC engine.
Also, the timer is disabled for factory configurations. Functional errors
should not exist in the factory configuration since it is stored and
validated during production and is never updated remotely.
8–20
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008