EP2S180F1020C4 Datasheet, PDF (456/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Stratix II and Stratix II GX I/O Standards Support
with low EMI requirements or noise immunity requirements. The LVDS
standard does not require an input reference voltage. However, it does
require a 100- termination resistor between the two signals at the input
buffer. Stratix II and Stratix II GX devices provide an optional 100-
differential LVDS termination resistor in the device using on-chip
differential termination. Stratix II and Stratix II GX devices support both
input and output levels operation.
Differential LVPECL
The low-voltage positive (or pseudo) emitter coupled logic (LVPECL)
standard is a differential interface standard requiring a 3.3-V V_CCIO. The
standard is used in applications involving video graphics,
telecommunications, data communications, and clock distribution. The
high-speed, low-voltage swing LVPECL I/O standard uses a positive
power supply and is similar to LVDS. However, LVPECL has a larger
differential output voltage swing than LVDS. The LVPECL standard does
not require an input reference voltage, but it does require a 100-
termination resistor between the two signals at the input buffer.
Figures 4–18 and 4–19 show two alternate termination schemes for
LVPECL.
1
Stratix II and Stratix II GX devices support both input and
output levels operation.
Figure 4–18. LVPECL DC Coupled Termination
Output Buffer
Z = 50 Ω
Input Buffer
100 Ω
Z = 50 Ω
Figure 4–19. LVPECL AC Coupled Termination
Output Buffer
10 to 100 nF
Z = 50 Ω
V_CCIO
V_CCIO
R1
R1
100 Ω
10 to 100 nF _{Z = 50 Ω}
R2
R2
Input Buffer
4–18
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008