EP2S180F1020C4 Datasheet, PDF (545/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

DSP Blocks in Stratix II and Stratix II GX Devices
Figure 6–13. Four-Multiplier Adder Mode
shiftina
shiftinb
mult_round (1)
mult_saturate (1)
signa (1)
signb (1)
aclr[3..0]
clock[3..0]
ena[3..0]
Data A 1
Data B 1
DQ
ENA
CLRN
DQ
ENA
CLRN
Q1.15
Round/
Saturate
(4)
PRN
DQ
ENA
CLRN
PRN
DQ
ENA
CLRN
Data A 2
Data B 2
DQ
ENA
CLRN
DQ
ENA
Q1.15
Round/
Saturate
(4)
PRN
DQ
ENA
CLRN
PRN
DQ
ENA
CLRN
Data A 1
Data B 1
DQ
ENA
CLRN
DQ
ENA
CLRN
Q1.15
Round/
Saturate
(4)
PRN
DQ
ENA
CLRN
PRN
DQ
ENA
CLRN
Data A 2
Data B 2
DQ
ENA
CLRN
DQ
ENA
Q1.15
Round/
Saturate
(4)
PRN
DQ
ENA
CLRN
PRN
DQ
ENA
CLRN
PRN
DQ
ENA
CLRN
Adder/
Subtractor/
Accumulator
1
Q1.15
Rounding
(4)
addnsub1 (2)
addnsub1/3_round (2)
signa (2)
signb (2)
addnsub3 (2)
PRN
DQ
ENA
CLRN
Adder
DQ
ENA
CLRN
PRN
DQ
ENA
CLRN
Adder/
Subtractor/
Accumulator
1
Q1.15
Rounding
(4)
PRN
DQ
ENA
CLRN
mult0_is_saturated (3)
mult1_is_saturated (3)
Data Out 1
mult0_is_saturated (3)
mult1_is_saturated (3)
shiftoutb shiftouta
Notes to Figure 6–13:
(1) These signals are not registered or registered once to match the data path pipeline.
(2) You should send these signals through the pipeline register to match the latency of the data path.
(3) These signals match the latency of the data path.
(4) The rounding and saturation is only supported in 18- × 18-bit signed multiplication for Q1.15 inputs.
Altera Corporation
January 2008
6–29
Stratix II Device Handbook, Volume 2