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EP2S180F1020C4 Datasheet, PDF (254/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1 | |||
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Contents
Stratix II Device Handbook, Volume 2
References ............................................................................................................................................. 4â42
Referenced Documents ....................................................................................................................... 4â43
Document Revision History ............................................................................................................... 4â44
Chapter 5. High-Speed Differential I/O Interfaces with DPA in Stratix II and Stratix II GX
Devices
Introduction ............................................................................................................................................ 5â1
I/O Banks ................................................................................................................................................ 5â1
Differential Transmitter ........................................................................................................................ 5â6
Differential Receiver .............................................................................................................................. 5â8
Receiver Data Realignment Circuit ............................................................................................... 5â9
Dynamic Phase Aligner ................................................................................................................. 5â10
Synchronizer ................................................................................................................................... 5â12
Differential I/O Termination ............................................................................................................. 5â12
Fast PLL ................................................................................................................................................ 5â13
Clocking ................................................................................................................................................ 5â14
Source Synchronous Timing Budget ........................................................................................... 5â16
Differential Data Orientation ........................................................................................................ 5â17
Differential I/O Bit Position ......................................................................................................... 5â17
Receiver Skew Margin for Non-DPA .......................................................................................... 5â19
Differential Pin Placement Guidelines ............................................................................................. 5â21
High-Speed Differential I/Os and Single-Ended I/Os ............................................................. 5â21
DPA Usage Guidelines .................................................................................................................. 5â22
Non-DPA Differential I/O Usage Guidelines ............................................................................ 5â26
Board Design Considerations ............................................................................................................ 5â27
Conclusion ............................................................................................................................................ 5â28
Referenced Documents ....................................................................................................................... 5â29
Document Revision History ............................................................................................................... 5â29
Section IV. Digital Signal Processing (DSP)
Revision History .................................................................................................................... Section IVâ1
Chapter 6. DSP Blocks in Stratix II and Stratix II GX Devices
Introduction ............................................................................................................................................ 6â1
DSP Block Overview ............................................................................................................................. 6â1
Architecture ............................................................................................................................................ 6â8
Multiplier Block ................................................................................................................................ 6â8
Adder/Output Block ..................................................................................................................... 6â16
Operational Modes .............................................................................................................................. 6â21
Simple Multiplier Mode ................................................................................................................ 6â22
Multiply Accumulate Mode ......................................................................................................... 6â25
Multiply Add Mode ....................................................................................................................... 6â26
Software Support ................................................................................................................................. 6â32
Conclusion ............................................................................................................................................ 6â32
Referenced Documents ....................................................................................................................... 6â33
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Altera Corporation
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